In a high speed digital circuit, the major noise is a power/ground bounce noise of an input/output end. Generally, when the output end of an output buffer is switching status, a power/ground bounce noise is derived from the flow of intense current through the parasitic inductance of the bonding wires, lead frame or pin. Please refer to FIG. 1 which is a schematic diagram showing conventional output buffers commonly electrically connected to a power voltage Vpp and a ground voltage Vss. The common voltage source of the output buffers 701˜70n is connected to a pad via a pin and a bonding wire. Meanwhile, the parasitic inductances of the pin and pad/bonding wire are generated, and the equivalent inductance is represented by an inductor L1. Similarly, there is inductance equivalent to the parasitic inductances of the pin and pad/bonding wire between the output buffers 701˜70n and a ground Vss, which is represented by L2.
Since there are parasitic inductors L1 and L2 existing between the output buffers 701˜70n and the voltage source and ground, respectively, a power/ground bounce noise may occur when some of the output buffers 701˜70n change their output status. For example, when the output status of the output buffers 701 and 702 is switched from a low level to a high level, the power voltage Vpp provides a driving current to the output buffers 701 and 702. At that moment, the instaneous change of the current causes an instaneous voltage drop of the parasitic inductor L1, which is represented by the equation of ΔV1=L1·di/dt. Hence, all the output buffers 701˜70n receive a power voltage of (Vpp−ΔV1). Even for the output buffer 70n−1 to maintain at the high level, the voltage thereof is decreased with the voltage drop resulting from the status-switching of the output buffers 701 and 702. It is so-called as power bounce noise. On the other hand, when the output status of the output buffers 701 and 702 changes from the high level to the low level, a discharge current will be provided from the output buffers 701 and 702 to ground. Such instaneous current change also results in an instaneous voltage drop (ΔV2=L2×di/dt) on the parasitic inductor L2, so the ground voltage received by the output buffers 701˜70n becomes (Vss+ΔV2). Meanwhile, for the output buffer 70n to maintain at the low level, the voltage thereof increases with the ground voltage drop, which is so-called as ground bounce noise. Those power/ground bounce noises possibly result in an erroneous signal. Moreover, the more output buffers are switching their output status at the same time, the more power/ground bounce noises occur.
Please refer to FIG. 2 which shows a conventional circuit design of one of the output buffers of FIG. 1. The input signals Dp and Dn are transmitted to NOT gates 72 and 74, respectively. The outputs of the NOT gates 72 and 74 are transmitted to gate electrodes of a P-channel metal-oxide-semiconductor (PMOS) transistor mp1 and a N-channel metal-oxide-semiconductor (NMOS) transistor mn1, respectively. The source electrode of the PMOS transistor mp1 is coupled to the voltage source while the drain electrode thereof is coupled to the output end OUT for generating an output signal Do. The source electrode of the NMOS transistor mn1 is coupled to ground while the drain electrode thereof is coupled to the output end.
For obtaining a high speed effect of the output buffer, the channel width of the MOS transistors mp1 and mn1 of the output buffer is required to be large enough for complying with large driving current and discharge current in the prior art. As is known, large current of the MOS transistor means lower equivalent resistance. Hence, when the power voltage and the ground voltage vary, larger power/ground bounce noises occur in case of larger current involved. Once the amplitude of the output end varies too much, it is possible to cause an error.
On the other hand, if the channel width of the MOS transistors in the output buffer is narrowed down in order to reduce power/ground bounce noises, the capability of the MOS transistors to generate the driving current and the discharge current is adversely effected. Thus the transmission rate and the performance are unsatisfactory.
Therefore, the purpose of the present invention is to take both advantages of high transmission rate and low power/ground bounce noises.